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features ? read access time ? 200 ns ? automatic page write operation ? internal address and data latches for 256 bytes ? internal control timer ? fast write cycle time ? page write cycle time ? 10 ms maximum ? 1 to 256 byte page write operation ? low power dissipation ? 50 ma active current ? hardware and software data protection ? data polling for end of write detection ? high reliability cmos technology ? endurance: 10,000 cycles ? data retention: 10 years ? single 5v 10% supply ? cmos and ttl compatible inputs and outputs ? jedec approved byte-wide pinout 1. description the at28c040 is a high-performance elec trically erasable and programmable read- only memory (eeprom). its 4 megabits of memory is organized as 524,288 words by 8 bits. manufactured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 200 ns with power dissipation of just 440 mw. the at28c040 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 256-byte page register to allow writing of up to 256 bytes simultaneously. during a write cycle, the address and 1 to 256 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected, a new access for a read or write can begin. atmel's at28c040 has additional features to ensure high quality and manufacturabil- ity. the device utilizes internal error co rrection for extended en durance and improved data retention characteristics. an optional software data protection mechanism is available to guard against inadvertent writ es. the device also in cludes an extra 256 bytes of eeprom for device identification or tracking. 4-megabit (512k x 8) paged parallel eeproms at28c040 0542f?peepr?2/09
2 0542f?peepr?2/09 at28c040 2. pin configurations 2.1 44-lead lcc ? top view pin name function a0 - a18 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 a12 a7 a6 a5 nc nc nc a4 a3 a2 a1 a13 a8 a9 a11 nc nc nc nc oe a10 ce 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 a0 i/o0 i/o1 i/o2 vss nc i/o3 i/o4 i/o5 i/o6 i/o7 a15 a16 a18 nc nc nc vcc we nc a17 a14 2.2 32-lead flatpack ? top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a17 a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3
3 0542f?peepr?2/09 at28c040 3. block diagram 4. absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v
4 0542f?peepr?2/09 at28c040 5. device operation 5.1 read the at28c040 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual-line control gives designers flexibility in prev enting bus contention in their systems. 5.2 byte write a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is la tched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . once a byte write has be en started, it will automati - cally time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectiv ely be a polling operation. 5.3 page write the page write operation of the at28c040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 255 additional bytes. each successive byte must be written within 150 s (t blc ) of the previous byte. if the t blc limit is exceeded, the at28c040 will cease accept ing data and commence the internal program - ming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a8 - a18 inputs. for each we high to low transition during the page write operation, a8 - a18 must be the same. the a0 to a7 inputs specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are spec - ified for writing will be wr itten; unnecessary cycling of other by tes within the page does not occur. 5.4 data polling the at28c040 features data polling to indicate the end of a wr ite cycle. during a byte or page write cycle an attempted read of the last byte wr itten will result in the co mplement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. 5.5 toggle bit in addition to data polling, the at28c040 provides another method for determining the end of a write cycle. during the write operation, successiv e attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop tog - gling and valid data will be read. reading the toggle bi t may begin at any ti me during the write cycle. 5.6 data protection if precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. atmel ? has incorporated both hardware and software fe atures that will protect the memory against inadvertent writes.
5 0542f?peepr?2/09 at28c040 5.6.1 hardware protection hardware features protect against inadvertent writes to the at28c040 in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical) the wr ite function is inhibited; (b) v cc power-on delay ? once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit ? holding any one of oe low, ce high or we high inhibits write cycles; (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. 5.6.2 software data protection a software controlled data protection feature has been implemented on the at28c040. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28c040 is shipped from atmel with sdp disabled. sdp is enabled when the host system issues a se ries of three write commands; three specific bytes of data are written to three specific addresses (refer to software data protection algo - rithm). after writing the 3-byte command sequence and after t wc , the entire at28c040 will be protected against inadvertent write operations. it should be noted that once protected, the host can still perform a byte or page write to the at28c040. to do so, the same 3-byte command sequence used to enable sdp must precede the data to be written. once set, sdp will remain acti ve unless the disable command sequence is issued. power transi - tions do not disable sdp, and sdp will protect the at28c040 during pow er-up and power-down conditions. all command sequences must conform to the page write timing specifications. the data in the enable and disable command sequences is not written to the device, and the memory addresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device without the 3-byte comma nd sequence will start the internal write timers. no data will be wr itten to the device; however, for the duration of t wc , read operations will effect ively be polling operations. 5.7 device identification an extra 256 bytes of eeprom memory are availabl e to the user for device identification. by raising a9 to 12v 0.5v and using address locations 7ff80h to 7ffffh, the bytes may be writ - ten to or read from in the same manner as the regular memory array. 5.8 optional chip erase mode the entire device can be erased using a 6-byte software erase code. please see software chip erase application note for details.
6 0542f?peepr?2/09 at28c040 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 6. dc and ac operating range at28c040-20 operation read program operating temperature (case) industrial -40c - 85c -40c - 85c extended -55c - 125c -40c - 85c v cc power supply 5v 10% 5v 10% 7. operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in write inhibit x x v ih write inhibit x v il x output disable x v ih x high z 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 a i lo output leakage current v i/o = 0v to v cc 10 a i cc v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage cmos i oh = -100 a; v cc = 4.5v 4.2 v
7 0542f?peepr?2/09 at28c040 10. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 11. input test waveform s and measurement level t r , t f < 5 ns 12. output test load note: 1. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter at28c040-20 units min max t acc address to output delay 200 ns t ce (1) ce to output delay 200 ns t oe (2) oe to output delay 0 55 ns t df (3)(4) ce or oe to output float 0 55 ns t oh output hold from oe , ce or address, whichever occurred first 0 ns 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 410pfv in = 0v c out 812pfv out = 0v
8 0542f?peepr?2/09 at28c040 15. ac write waveforms 15.1 we controlled 15.2 ce controlled 14. ac write characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )100ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns
9 0542f?peepr?2/09 at28c040 17. page mode write waveforms (1)(2) notes: 1. a8 through a18 must specify the page address during each high to low transition of we (or ce ). 2. oe must be high only when we and ce are both low. 16. page mode characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 s t wph write pulse width high 50 ns
10 0542f?peepr?2/09 at28c040 18. software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 256 bytes of data are loaded. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address enter data protect state writes enabled (2) 19. software data protection disable algorithm (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address load data 55 to address 2aaa exit data protect state (3) 20. software protected program cycle waveform (1)(2)(3) notes: 1. a0 - a14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a8 - a18) must be the same for each high to low transition of we (or ce ). 3. oe must be high only when we and ce are both low.
11 0542f?peepr?2/09 at28c040 notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. 22. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. 24. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 21. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns 23. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
12 0542f?peepr?2/09 at28c040 25. ordering information note: 1. sl703 requires testing to mil-883 standards; sl703 is marked on the package. 25.1 standard packaging t acc (ns) i cc (ma) ordering code package operation range active 200 50 at28c040-20fi 32f industrial (-40 to 85 c) at28c040-20li 44l 50 at28c040-20fi sl703 32f extended (see dc and ac operating range table) at28c040-20li sl703 44l package type 32f 32-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 44l 44-pad, non-windowed, ceramic leadless chip carrier (lcc) options blank standard device: endurance = 10k write cycles; write time = 10 ms
13 0542f?peepr?2/09 at28c040 26. packaging information 26.1 32f ? flatpack 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32f , 32-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) b 32f 10/21/03 dimensions in millimeters and (inches). controlling dimension: inches. jedec outline mo-115 aa pin #1 id 9.40(0.370) 6.86(0.270) 0.51(0.020) 0.38(0.015) 1.27(0.050) bsc 1.14(0.045) max 3.05(0.120) 2.49(0.098) 1.14(0.045) 0.66(0.026) 1.83(0.072) 0.76(0.030) 10.36(0.408) 9.02(0.355) 0.18(0.007) 0.10(0.004) 12.40(0.488) 11.99(0.472) 21.08(0.830) 20.60(0.811)
14 0542f?peepr?2/09 at28c040 26.2 44l ? lcc 16.81(0.662) 16.26(0.640) 16.81(0.662) 16.26(0.640) 2.74(0.108) 2.16(0.085) 2.03(0.080) 1.40(0.055) index corner 0.635(0.025) 0.381(0.015) x 45? 0.305(0.012) 0.178(0.007) radius 0.737(0.029) 0.533(0.021) 1.02(0.040) x 45? pin 1 1.40(0.055) 1.14(0.045) 2.41(0.095) 1.91(0.075) 2.16(0.085) 1.65(0.065) 12.70(0.500) bsc 1.27(0.050) typ 12.70(0.500) bsc dimensions in millimeters and (inches) controlling dimension: inches 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44l , 44-pad (0.600" wide), non-windowed, ceramic lid, leadless chip carrier (lcc) a 44l 04/11/01 mil-std-1835 c-5
0542f?peepr?2/09 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support p_eeprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2009 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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